Texas Instruments /MSP432E411Y /SYSCTL /DSCLKCFG

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Interpret as DSCLKCFG

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SYSCTL_DSCLKCFG_DSSYSDIV 0 (SYSCTL_DSCLKCFG_DSOSCSRC_PIOSC)SYSCTL_DSCLKCFG_DSOSCSRC 0 (SYSCTL_DSCLKCFG_MOSCDPD)SYSCTL_DSCLKCFG_MOSCDPD 0 (SYSCTL_DSCLKCFG_PIOSCPD)SYSCTL_DSCLKCFG_PIOSCPD

SYSCTL_DSCLKCFG_DSOSCSRC=SYSCTL_DSCLKCFG_DSOSCSRC_PIOSC

Description

Deep Sleep Clock Configuration Register

Fields

SYSCTL_DSCLKCFG_DSSYSDIV

Deep Sleep Clock Divisor

SYSCTL_DSCLKCFG_DSOSCSRC

Deep Sleep Oscillator Source

0 (SYSCTL_DSCLKCFG_DSOSCSRC_PIOSC): PIOSC

2 (SYSCTL_DSCLKCFG_DSOSCSRC_LFIOSC): LFIOSC

3 (SYSCTL_DSCLKCFG_DSOSCSRC_MOSC): MOSC

4 (SYSCTL_DSCLKCFG_DSOSCSRC_RTC): Hibernation Module RTCOSC

SYSCTL_DSCLKCFG_MOSCDPD

MOSC Disable Power Down

SYSCTL_DSCLKCFG_PIOSCPD

PIOSC Power Down

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